This invention finds use in digital radio communications systems where the receive signal demodulator oscillator is phase synchronized with the transmitter oscillator. It is particularly well suited to obtaining fast synchronization or locking and subsequently maintaining lock in the presence of burst noise and when the received power level is very low, that is where the receive signal power level is very near to a minimum Carrier to Noise (C/N) ratio that is needed for communications to occur. Such conditions occur in communications systems using satellite communications technology; in distant radio communications where transmitter power is either expensive to provide, such as in a remote location, or is limited by spectrum licensing or regulation to a maximum power level; and in fibre optic communication where maximum distances between repeater sites is needed (e.g. undersea cables).
A problem in modern digital communications is knowing when the demodulator is in and out of lock with the transmitter. Knowing the lock condition enables the designer to implement bandwidth switching in the demodulator to help incorporate fast locking (wide bandwidth) and secure locking (narrow bandwidth). Present lock detect circuits are incorporated at the IF demodulator, and have problems of cost, implementation, and reliability in low C/N operation.
When the communications signal is encoded with forward error correction, it is possible to implement a lock detect circuit based upon the quality of the received data. This method of obtaining bandwidth switching provides several benefits:
high reliability based on the received data;
a digital implementation which is simple and cost effective;
separate digitally setable wide-to-narrow and narrow-to-wide thresholds;
bandwidth switching which is cycle slip resistant.